1. Technical Field
The present disclosure relates to the fabrication of nanowires for interconnecting integrated circuits and, in particular, to improvements in performance and reliability of inter-layer dielectrics used in a dual damascene process.
2. Description of the Related Art
There has been widespread use of damascene interconnect structures in microcircuit fabrication since the late 1990s when the semiconductor industry shifted from aluminum to copper metallization. A damascene interconnect process forms inlaid copper wiring by first etching trenches in a dielectric material, and then filling the trenches with copper, typically using a plating process such as, for example, electroplating. Through the use of a damascene process, semiconductor manufacturers can avoid etching copper. The term “dual damascene” refers to a process in which vertically adjacent metal lines and vias connecting them are formed in the same dielectric layer. FIG. 1 shows an inlaid metal structure 80 formed by such a dual damascene process, in which metal lines 82 and 84 are connected by a via 86 formed in a dielectric layer 88. A dual damascene process permits filling the trench for the upper metal line 84, and the via 86, in the same metal deposition step. Dual damascene integration schemes can, for example, form the via 86 first, and then the trench for the upper metal line 84, and then fill both at the same time. Or, the trench for the upper metal line 84 can be formed first, and then the via 86. Typically, trenches are wider than vias, so that an element of the final interconnect structure that includes the upper metal line 84 and the via 86 resembles a “T” shape as shown in FIG. 1. Alternatively, the trench widths and the via width connecting the trenches may be of comparable size, in which case an element of the final interconnect structure above the lower metal line 82 resembles a straight column, or an “I” shape, instead of a “T” shape.
Current trends in the fabrication of dual damascene interconnect structures for integrated circuits include investigating mechanical properties of low dielectric constant (low-k) and ultra-low-k (ULK) dielectric materials used as insulation between the metal lines and the vias. Generally, it is desirable to use electrically insulating material that has a low dielectric constant, to reduce capacitance between adjacent nanowires. However, as the dielectric constant of such materials is reduced below a value of about 2.4 to achieve better electrical performance, the dielectric materials are becoming become more porous, with problematic consequences, as described below.
Illustrations of damascene structures that employ ULK inter-layer dielectrics as shown in FIGS. 2A-2D are found in an industry presentation given at Stanford University by the consortium Sematech International, entitled “Overview of Dual Damascene Cu/Low-k Interconnect.” A porous ULK dielectric film 90 used as an inter-layer dielectric is shown in FIG. 2A, as indicated by holes 92 distributed throughout the material. The holes 92 in this example are as large as several tens of nm across. Consequently, mechanical properties such as the Young's modulus, cohesive strength, and adhesion of such porous films are degraded. For example, the modulus of such a porous film scales with the dielectric constant such that ULK films have low modulus, whereas higher k films have a higher modulus. As the structural stability of the ULK dielectric film 90 becomes compromised, cracks 94 tend to form in response to film stress, as shown in FIG. 2B. Such cracking can occur when the ULK dielectric film 90 is subjected to thermal cycling or high pressure conditions during further processing of a semiconductor wafer, or during electronic packaging of a finished integrated circuit chip.
Another problem that tends to occur after etching ULK films is referred to as “dielectric flopover,” in which high aspect ratio structures 96 have been found to be unstable and tend to lean sideways as shown in FIG. 2C. As minimum dimensions shrink, vias, which provide vertical connections between adjacent metal lines, become tall and thin. Such structures that have a height-to-width ratio of greater than in the general range of 3 or 4 are referred to as high aspect ratio structures. It is more difficult for metal deposition processes to fill high aspect ratio vias, which results in metal voids 98 as shown in FIG. 2D. In summary, ULK dielectrics tend to be mechanically unstable, and are prone to have poor strength, poor adhesion, dielectric flopover, cracks, and voids.
FIG. 3 shows a table 100 in which material properties of ULK materials are compared with those of conventional silicon dioxide (SiO2) used as an inter-layer dielectric. With reference to the first and fifth rows of the table 100, it is seen that a reduction in the dielectric constant k from 2.2 to 1.03 is associated with an increase in porosity from 0 to about 50%. Accordingly, the modulus, hardness, and thermal conductivity of such ULK materials are each reduced by about a factor of 7, compared to conventional SiO2.